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Re: [ts-7000] TS7800 serial port delay

To:
Subject: Re: [ts-7000] TS7800 serial port delay
From: Arthur Roberts <>
Date: Mon, 9 Feb 2009 20:14:39 -0800 (PST)
Hello,

We have modified tsuart1.c as requested (using the kernel source supplied on the CD and the crosscompiler supplied: ts7800-crosstool-linux-gnueabi-2005q3-2), after uploading the tsuart1.ko onto the board and placing it in the right /lib/modules/... we can them rmmod the tsuart1 and tsuart7800 and then modprobe the new tsuart1 and tsuart7800. We can confirm we have done so by looking at printk messages in dmesg. However this results in a segmentation fault when trying to change port parameters. We note that it appears that the board doesn't load the module placed in /lib/modules/... and rather uses its own original tsuart1.ko via some sort of initrd-based process, so the only way to use our re-cross-compiled module is to do rmmod/modprobe. Can you please help us by providing a bit more information on how to replace the kernel module on the board in the proper way? Or alternatively help us get this new latency setting working one way or another. :-)

Thanks,
Arthur.


From: Michael Schmidt <>
To:
Sent: Tuesday, February 10, 2009 6:25:13 AM
Subject: Re: [ts-7000] TS7800 serial port delay

arthur.roberts74 wrote:
> Hi,
>
> Can somebody help with changing serial port settings for TS-7800?
>
> I'm using FPGA-driven ttts7 and it works as expected.Problem is that
> there is about 7 msec delay in read() function. Port is open with
> O_NONBLOCK option, completely raw mode and if there is no data at
> input lines then read() returns immediately (VMIN and VTIME both set
> to 0). But if there are input signals then read() blocks for about 7
> msecs (measured with scope) before returning. Presumably delay is
> produced by serial port FIFO buffers to reduce CPU load as described
> in setserial() man and it is default setting for kernel
> (http://linux. about.com/ library/cmd/ blcmdl8_setseria l.htm).
>
> Question is, can this be changed? Did anybody tried to run setserial()
> for FPGA ports with "low_latency" parameter and did it really changed
> port settings?
> Board is running full Debian.

The low_latency option is supported in the latest xuart drivers (Linux
2.4). It has made it into our CVS tree for Linux 2.4 (tsuarts) however
I am not sure this has propogated further. It does not appear to be in
CVS for Linux 2.6 (tsuarts).

This option is actually handled at a layer above the serial port driver,
but it was found that for some reason when the upper layers call the
verify_port function (for the tsuarts this is implemented in tsuart0.c
for Linux 2.4, and tsuart1.c in Linux 2.6; the xuart drivers only have a
single module), it had some expectation regarding ser->baud_base which
had to be true before it would honor the low_latency option. Not
knowing this, our drivers' original coding did not meet this expectation.

The following lines of code, when added to tsuart_verify_ port() (or
xuart_verify_ port()), were found to make the upper layers happy:
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
// new code follows
if (ser->baud_base < 9600) {
ser->baud_base = 115200; // required to allow ioctl to set low_latency
}

With this in place, I have found that latency is drastically reduced...
I don't recall the exact figures but if I remember correctly it was
close to an order of magnitude faster (e.g. 800us versus 8ms)

> Regards,
> Arthur

______ Best Regards,
|__ __/ Michael Schmidt
|| Software Engineer
||echnologic Systems (EmbeddedARM. com)
|| (480) 16525 East Laser Drive
|/ 837-5200 Fountain Hills, AZ 85268
http://oz.embeddeda rm.com/~michael




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