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[ts-7000] TS7800 serial port delay

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Subject: [ts-7000] TS7800 serial port delay
From: "arthur.roberts74" <>
Date: Sun, 08 Feb 2009 00:22:13 -0000
Hi,

Can somebody help with changing serial port settings for TS-7800? 

I'm using FPGA-driven ttts7 and it works as expected.Problem is that
there is about 7 msec delay in read() function. Port is open with
O_NONBLOCK option, completely raw mode and if there is no data at
input lines then read() returns immediately (VMIN and VTIME both set
to 0). But if there are input signals then read() blocks for about 7
msecs (measured with scope) before returning. Presumably delay is
produced by serial port FIFO buffers to reduce CPU load as described
in setserial() man and it is default setting for kernel
(http://linux.about.com/library/cmd/blcmdl8_setserial.htm).

Question is, can this be changed? Did anybody tried to run setserial()
for FPGA ports with "low_latency" parameter and did it really changed
port settings?
Board is running full Debian.


Regards,
Arthur



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