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Re: [ts-7000] TS7800 serial port delay

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Subject: Re: [ts-7000] TS7800 serial port delay
From: Michael Schmidt <>
Date: Mon, 09 Feb 2009 10:25:13 -0700
arthur.roberts74 wrote:
> Hi,
> 
> Can somebody help with changing serial port settings for TS-7800? 
> 
> I'm using FPGA-driven ttts7 and it works as expected.Problem is that
> there is about 7 msec delay in read() function. Port is open with
> O_NONBLOCK option, completely raw mode and if there is no data at
> input lines then read() returns immediately (VMIN and VTIME both set
> to 0). But if there are input signals then read() blocks for about 7
> msecs (measured with scope) before returning. Presumably delay is
> produced by serial port FIFO buffers to reduce CPU load as described
> in setserial() man and it is default setting for kernel
> (http://linux.about.com/library/cmd/blcmdl8_setserial.htm).
> 
> Question is, can this be changed? Did anybody tried to run setserial()
> for FPGA ports with "low_latency" parameter and did it really changed
> port settings?
> Board is running full Debian.

The low_latency option is supported in the latest xuart drivers (Linux 
2.4).  It has made it into our CVS tree for Linux 2.4 (tsuarts) however 
I am not sure this has propogated further. It does not appear to be in 
CVS for Linux 2.6 (tsuarts).

This option is actually handled at a layer above the serial port driver, 
but it was found that for some reason when the upper layers call the 
verify_port function (for the tsuarts this is implemented in tsuart0.c 
for Linux 2.4, and tsuart1.c in Linux 2.6; the xuart drivers only have a 
single module), it had some expectation regarding ser->baud_base which 
had to be true before it would honor the low_latency option.   Not 
knowing this, our drivers' original coding did not meet this expectation.

The following lines of code, when added to tsuart_verify_port() (or 
xuart_verify_port()), were found to make the upper layers happy:
   if (ser->irq < 0 || ser->irq >= NR_IRQS)
     ret = -EINVAL;
   // new code follows
   if (ser->baud_base < 9600) {
     ser->baud_base = 115200; // required to allow ioctl to set low_latency
   }

With this in place, I have found that latency is drastically reduced... 
I don't recall the exact figures but if I remember correctly it was 
close to an order of magnitude faster (e.g. 800us versus 8ms)

> Regards,
> Arthur

  ______   Best Regards,
|__  __/                  Michael Schmidt
    ||                   Software Engineer
    ||echnologic Systems (EmbeddedARM.com)
    || (480)        16525 East Laser Drive
    |/ 837-5200   Fountain Hills, AZ 85268
        http://oz.embeddedarm.com/~michael


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