[ts-7000] Re: Opencore/usercore bug with headerpin inputs?

["bulent.selek" <>]

I don't know what the problem is with ts7300_opencore but, yes, you
are correct.

I overcame the problem with a simple solution, all the dio1 lines for
inputs and the dio2's for outputs.

If you want to use this solution, you have to modify module's pin
definitions like

// inout reg [4:0] blue_pad // REMOVE THIS LINE, 
input [4:0] blue_pad; 
// inout reg [4:0] red_pad; // REMOVE THIS LINE
input [4:0] red_pad; 
// inout reg [4:0] green_pad; // REMOVE THIS LINE
input [4:0] green_pad;

and modify the body

always @(headerpin_o or headerpin_oe or blue_pad or green_pad or
red_pad or
  dio10to17_pad or dio0to8_pad or dio9_pad or vsync_pad or hsync_pad)
begin
//  blue_pad = 5'bzzzzz;  // REMOVE THIS LINE
//  red_pad = 5'bzzzzz;  // REMOVE THIS LINE
//  green_pad = 5'bzzzzz; // REMOVE THIS LINE
  for (i = 0; i < 5; i = i + 1) begin
    headerpin_i[1 + (i * 2)] <= blue_pad[i];
    headerpin_i[11 + (i * 2)] <= green_pad[i];
    headerpin_i[4 + (i * 2)] <= red_pad[i];
//    if (headerpin_oe[1 + (i * 2)]) // REMOVE THIS LINE 
//      blue_pad[i] = headerpin_o[1 + (i * 2)]; // REMOVE THIS LINE
//    if (headerpin_oe[11 + (i * 2)]) // REMOVE THIS LINE
//      green_pad[i] = headerpin_o[11 + (i * 2)]; // REMOVE THIS LINE
//    if (headerpin_oe[4 + (i * 2)]) // REMOVE THIS LINE
//      red_pad[i] = headerpin_o[4 + (i * 2)]; // REMOVE THIS LINE
  end


now, dio1's most lines (blue, red and green pads) are ready for input. 
you can also repeat the operation for vsync and hsync pads.



Bulent





--- In  "jpeshkin" <> wrote:
>
> 
> I'm a Verilog newbie, but it seems that a usercore cannot use a
> headerpin (the DIO2 header) as an input without correcting a bug in
> ts7300_top.
> 
> All my attempts to use pint as inputs failed (always read a zero)
> until I moved the dio0to8_pad = 9'bzzzzzzzzz statement to a point
> after the headerpin_i had copied the input value.
> 
> Am I correct that there is a problem here?
>



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