--- In "gebbet00" <> wrote:
>
> I've observed that state of DIO_14 is undetermined after power up. Is
> that easily fixable? I'd like if to be either input or output with a
> zero value. That's because I want to use that pin to enable power
> output just after I've reset output registers so I don't have outputs
> randomly activated after power up.
>
> Is that random state of DIO_14 a bug or a feature?
>
> Thanks in advance
>
I think I've found the issue.
When completely disconnected, GPBUS behaves as expected, making DIO_x
inputs. But when there are certain signals present at DIO_0-7, logic
goes crazy and makes at least DIO_14 an output with an uncertain state.
My design connected GPBUS to a latch through a 74LVC245. But the latch
wasn't a 74HC373 as recommended but a 74LS373. Since DIR pin of
74LVC254 was connected to GPBUS RD#, it connected internal bus to
GPBUS and LS373's TTL inputs created noise signals at internal bus
that were fed to TS-7400, which seems to created DIO_14 mess.
The solution? An elegant pullup at 74LVC245's DIR so direction is
forced inwards, from GPBUS to internal bus until RD# controls it. That
ways there aren't random signals at GPBUS' inputs and no strange behavior.
Hopefully TS engineers will take note and check CPLD programming.
------------------------------------
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> Your email settings:
Individual Email | Traditional
<*> To change settings online go to:
http://groups.yahoo.com/group/ts-7000/join
(Yahoo! ID required)
<*> To change settings via email:
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|