thanks alot, it really helped.
--- In David Hawkins <> wrote:
>
> mugilan wrote:
> > Hi,
> >
> > I am a student in Georgia Tech. I recently bought a TS7300 board and I
> > need to implement a high speed data acquisition machine within the
> > FPGA. I think the best way is to use the Block Memory within the FPGA
> > and implement a Single Port Single Clock because I need to accumulate
> > about 1.5kb of data at one time.
> >
> > I could not do it using logic cells as memory array because this uses
> > more than the available logic elements. My problem is I do not know
> > how to declare the block memory. I have looked at the Altera
> > documentations on Block Memory and I pretty much how to manipulate the
> > signals (byteena, wren, datain, dataout, clock, addresstall, address,
> > enable and such) to implement it but I still dont know how to declare
> > it yet.
> >
> > If anyone can help me with this, it would be great. Also, if you have
> > any other suggestion, i am open for ideas. Thank you.
>
> See below for a cut-and-paste example.
>
> I typically use the MegaWizard and select the component, and then
> cut the definition out of the file it generates. The altsyncram is
> in the megafunctions library, so VHDL code requires this at the top:
>
> -- Altera Megafunction components
> library altera_mf;
> use altera_mf.altera_mf_components.all;
>
> Cheers,
> Dave
>
>
>
> -- ------------------------------------------------------------
> -- RAM
> -- ------------------------------------------------------------
> --
> -- The generics for the RAM were determined using the
> -- MegaWizard on a couple of example single-ported RAM
> -- designs. Only the generics and ports that are required
> -- for single-ported operation are used.
> --
> u4: altsyncram
> generic map (
> -- RAM size
> numwords_a => 2**RAM_ADDR_WIDTH,
> widthad_a => RAM_ADDR_WIDTH,
> width_a => 32,
> width_byteena_a => 4,
> byte_size => 8,
>
> -- RAM type
> operation_mode => "SINGLE_PORT",
>
> -- RAM output registers
> outdata_aclr_a => "CLEAR0",
> outdata_reg_a => "CLOCK0",
>
> -- Targeted device
> --
> -- unused supports BYTE_SIZE 8 or 9
> -- intended_device_family => "unused",
> intended_device_family => "Stratix II",
> -- intended_device_family => "Cyclone II",
>
> -- Implementation
> implement_in_les => "OFF",
> ram_block_type => "AUTO",
> -- ram_block_type => "M-RAM",
> -- ram_block_type => "M4K",
> -- ram_block_type => "M512",
>
> -- As generated by the MegaWizard
> lpm_hint => "ENABLE_RUNTIME_MOD=NO",
> lpm_type => "altsyncram"
> )
> port map (
> clock0 => clk,
> aclr0 => rst,
> wren_a => ram_we,
> address_a => ram_addr,
> byteena_a => ram_byteen,
> data_a => ram_d,
> q_a => ram_q
> );
>
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