Hi Jason,
> Thanks for your input!
No problem!
> our verification platform that I am using is done with Cadence, so in theory
> my verilog code can be compiled in Quartus but then would have to be ported
> back into linux land.
Quartus works fine under Linux ... oh, but thats probably not the
web edition ... I have both full and web installed. If you're
at (or affiliated with) a university, you can get a full license
without too much trouble.
> I will have to run many simulations with other pieces
> of the design as well as incorporate more.
>
> Why wouldn't I receive the same error if done using Quartus II? After all,
> it is just verilog, right?
Nope. Its a black box :)
Altera FPGA-specific components are hidden from you. The RAM, PLL,
etc components have verilog wrappers, VHDL wrappers, etc, but
you never see a file with their implementation.
They do however provide simulation models. I use ModelSim-AE (Altera
Edition) where the libraries are compiled in by default, and I
also use ModelSim SE, where I have to compile the libraries
explicitly. Altera's Quartus II Handbook describes what to do
in Volume 3 ... if my memory serves me right ...
> If I can help it -I would rather use Cadence and just pass the edif
> into Quartus for synthesis and P&R.
Yep, it should be fine. You just need to figure out how to get
the Cadence tool to play nicely. For simulation it needs to pickup
the simulation versions, and for synthesis it needs to use
black-boxes for the components it does not know about.
I've done this for synthesis with Mentor Precision RTL and
Leonardo, so it'll be similar for Cadence. Look for
library mapping files, and probably read the Altera Quartus
handbook sections for your tool.
Altera is pretty good about responding to support requests too.
Cheers,
Dave
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