Bulent,
Did have another higher level VHDL wrapper file (complete
with 'COMPONENTs') that map/tie the VHDL file to the ts7300_top verilog
file? The COMPONENT in the VHDL would match the verilog module name.
tia
--- In "bulent.selek" <> wrote:
>
> Hi,
> We have the same feelings about verilog. :)
> I used mixed languages with quartus.
> Here is the part of my hdl files,
> first file is usercore entity in vhdl, based on ts7300_top.v, sdram
> pads included :)
> and the second is modified ts7300_top.v.
>
> Bulent Selek
>
>
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