Bulent,
Thank you very much. This will certainly help. I will share with you
my code is when I get it completed.
Do you use the VGA functionality within the FPGA or did you just keep
the pin definitions there in the verilog ts7300_top.v ?
I do not plan on using the VGA. I plan on implementing custom code and
outputting them on pins currently occupied by VGA pin definitions.
hockeyjo
--- In "bulent.selek" <> wrote:
>
> Hi,
> We have the same feelings about verilog. :)
> I used mixed languages with quartus.
> Here is the part of my hdl files,
> first file is usercore entity in vhdl, based on ts7300_top.v, sdram
> pads included :)
> and the second is modified ts7300_top.v.
>
> Bulent Selek
>
>
------------------------ Yahoo! Groups Sponsor --------------------~-->
Check out the new improvements in Yahoo! Groups email.
http://us.click.yahoo.com/4It09A/fOaOAA/yQLSAA/CFFolB/TM
--------------------------------------------------------------------~->
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> Your email settings:
Individual Email | Traditional
<*> To change settings online go to:
http://groups.yahoo.com/group/ts-7000/join
(Yahoo! ID required)
<*> To change settings via email:
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|