>... but it appears that the implementation of the
>serial driver on the EP3901 does not send a serial break using the linux
>command
>tcsendbreak(fd,0).
>
>Is this the confirmed by others?
There are two serial drivers for the 7260.
The driver for the serial ports built into the CPU is
drivers/serial/ep93xx_amba.c. It has code in it that looks like it can
send a break. (I did not try it.) This is /dev/ttyAM0 and /dev/ttyAM1.
The driver for the serial port in the FPGA is drivers/serial/tsuart.c; it
contains the code:
static void tsuart_break_ctl(struct uart_port *port, int break_state)
{
// UART does not support BREAK
If I remember correctly, the device files for this driver are
/dev/ttyTS[0-2].
A break condition usually just means that the serial receiver saw a 0
bit where it expected a stop bit. You can simulate this condition by
lowering the bit rate and sending a 00 byte.
For example, if you are using 19200 bps, you can set the bit rate to
9600 bps, send a 00, wait briefly, then set the bit rate back to 19200.
Since the 9600 bps bits are twice as long, only half of the zero bits have
been transmitted by the time the receiver is looking for the stop bit.
The receiver sees a 0 for the stop bit and detects a break.
Mark S.
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