Finally, I've to leave the I2S controller to realize a pseudo fast SPI
slave. A problem occur :
With the I2S controller, you must receice left and right channel. The
controller (shift register) can't be flush, only the fifo, so dead
data can be present in the first channel. In my project, it's not
acceptable, so I forgot the I2S controller ... the only solution is
the SSP in SPI slave.
I've tried with a other MCU and board (SBC-x270 with the xscale
PXA270), and the SPI work very well in slave ...
I really want to work with the TS board, TS make very good work for
embedded application (like the very fast boot mode !! less 2 sec to
start to the prompt is by far a very good performance !) but I need
3MHz slave SPI ...
Is somebody already succeeded in using SSP controller in SPI slave
with the EP93xx ?
If not , I will have to use an other board with xscale :-((
--- In "suptouch" <> wrote:
>
>
> Yes it's clear that tha received data are shifted. In master mode,
> it's work ! but in slave I really think there is a hard bug on the
> data synchronization
>
> I've tested with the same configuration but with the I2S controller on
> the EP9302. This controller is done for stereo audio acquisition. The
> bus is like the SPI but with a extra signal to indicate if the data is
> a left or a right signal. So I've : the data, the data clock and the
> Left/Right clock. We can only choose, 16, 24 or 32 bit data lengh, my
> need is 16.
> To push a new data in the fifo, it need to send the right and the left
> signal.
>
> This controller is mutch binding in using but work very well. I've
> tested to catch a full flow af data at 3MHz, in slave mode, by receive
> interrupt on I loss nothing.
>
> Thin controller can be mapped on the SSP pin or the AC97 pin.
>
> So in your ep93xx design, if you need a slave synchronous link,
> perhaps it can be a good solution ... For the TS7000 product, you can
> use it on he pin header, instead of the SPI signal.
>
>
>
> > Perhaps you missed something in your tests. From the data you
> > posted, it is clear that you are receiving your data, it just has one
> > extra bit clocked on at the end. The SPI transfer is a short, well
> > defined event. How close is the /ss signal to the clock last clock
> > edge 1) at low frequency 2) high frequency? What is generating
> > the /ss signal? You should really count the number of clock edges
> > (pos or neg -what ever you use) that are within the /ss period, with
> > a scope. If the signals are generated by an external master, those
> > settings should be checked too. To confirm the 'extra clock' theory
> > you could use a few values that will give well defined bit patterns.
> > If you send 0x0001, I expect you will get 0x0002. 0x0080 -> 0x0100 ...
>
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