http://www.opencores.com/
Viron.
--- waggywagz <> wrote:
> --- In "aqueisser"
> <> wrote:
> --- snip ---
> > Now I'm on the path to creating my own FPGA code
> and I was wondering
> > if anyone has some tutorial-type samples I could
> play with. I'm in the
> > process of learning Verilog and I'm also new to
> the Wishbone bus so it
> > would be great if anyone has some samples to look
> at.
> --- snip ---
>
> I was hoping someone else would answer this, since
> I, too could use a
> pointer or two to some good references, including a
> good reference
> book. Meanwhile, I've been noodling around off of
> the following sources.
>
> Verilog Tutorial
> http://www.asic-world.com/verilog/veritut.html
> [Idiosyncratic and incomplete, but helpful.]
>
> fpga4fun Projects
> http://www.fpga4fun.com/
> [Good, fairly simple, mostly hardware examples.]
>
> XESS Example Designs, Tutorials, Application Notes
> http://www.xess.com/ho03000.html
> [More extensive examples.]
>
> Also, as I recall the opencores.org site has a link
> to the wishbone spec.
>
> Hope this helps a bit.
> -David Wagner
>
> P.S. Although very much a hack at this point, if it
> might help I can
> post some working code fragments that move data from
> the ARM side
> through the wishbone bus and into FPGA blockram. I
> plan to post a
> complete, commented application to opencores.org
> once it is ready for
> public posting.
>
>
>
>
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