[ts-7000] Parking the KS8721 FPGA Ethernet Interface

["waggywagz" <>]

If someone has it handy, could you post the verilog (or even just the
signal levels) needed, to safely "park" the FPGA ethernet KS8721 chip
when it is not needed?  If it has not already been done, I can
cross-reference the KS8721 datasheet, the TS-7300 schematic, and the
ts7300_top.v source and post the resulting verilog here for review. 
If there are any 'gotchas' about turning off the KS8721, I would
appreciate finding out in advance.

Thanks.
-David Wagner





 
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