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[ts-7000] Re: new GNU openhardware ep9302 based SBC

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Subject: [ts-7000] Re: new GNU openhardware ep9302 based SBC
From: "pickanameanditstakensoihavethis" <>
Date: Sat, 06 May 2006 01:48:22 -0000
--- In  "Jesse Off" <> wrote: 
> 
> Interesting board.  Did you use all GNU/GPL software for schematic  
> capture and board layout also?   
>  
no gEDA is too mutch a pita to use at present  
it was done in protel dxp  
the gerber files will be released once the final prototype pcbs  
are ready to be ordered , don't want anyone attempting to make 1000 
possibaly faulty ones   
 
> BTW, Your LEDs are reversed biased on the schematic. 
 
ha always seem to manage that one ty for spotting it  
  
>  Curious as to why you put a diode inbetween 5V and the CF VCC 
like we did on the  
> TS-7200?   
>  
the cf card is removable and can be removed or inserted while power 
is still on, so its needed to provide some feedback suppresion  
 
i am curious as if the same reason was true for the use of it on the 
ts7200 as removing and inserting the cf on the ts7200 is not 
recommended while powered on , or is that bus isolation problem ? 
 
cpld should allow the needed isolation to remove or insert a CF card 
while the power is on , that may be the reason for the ts7200 not 
allowing it as it shares the data bus with the pc-104  
assuming the cf device is not a mounted file system at the time  
  
  
> I definitely look forward to seeing this hardware proven and any  
> subsequent software/hardware cores created.  Those will be GPL too  
> right?  We may manufacture this ourself (or quote it for custom  
> designs) if the BOM and manufacturing costs aren't too high.   
>  
well the licencing has been set to gnu gpl in order to cover  the 
software , ip cores and hardware , but the hardware may have to 
change to a more bsd like licence as it looks like a gpl will 
prevent  manufactuers form making a profit from manufactureing it, 
and as without profit it would not be worth making, that will need 
to be checked and changed to allow it, if it is the case  
 
 
> We hadn't seen that DVI chip before.  We may actually have a use 
for  
> that chip out here in the future.   
 
the dvi chip is a nice chip , was a pita to route  
all the pcb was manualy routed btw  
it should support 1240*1024 in digital or analog although  
i have attemped to follow the app notes for support of the higher 
1600*1240 hdtv compatable modes that requires a 165mhz clocking rate 
to the dvi chip , and a 800Mhz plus  serial data link to the dvi 
monitor,  
but the only practical way to see if that was managed would be to 
build it now  
 
its worth noteing there should be more than enough spare capacity in 
the fpga to allow for a mpeg video decoder ip core  
 
>  
> //Jesse Off 
>  
> --- In  "pickanameanditstakensoihavethis"  
> <donotsendmail@> wrote: 
> > 
> > hi            
> > well now the first step is done            
> > the initial schematics are now complete           
> >            
> > http://www.whipy.demon.co.uk/geep-sch.pdf          
> >           
> > and the coresponding pcb artwork           
> >           
> > http://www.whipy.demon.co.uk/geep.pdf          
> >           
> > we now would like some to look it over and let us know if there  
> are           
> > any potential problems before we commit to having the prototype  
> pcbs    
> > made            
> >           
> > the geep is a open source  GNU GPL licenced  unit           
> >           
> > it offers           
> >  ep9302  200Mhz arm cpu          
> >  up to 256MB of sdram        
> >  512MB of on board flash         
> >  T10/100 ethernet      
> >  2 * usb      
> >  rs232      
> >  ps/2     
> >  ac97 audio codec     
> >  ide     
> >  compact flash     
> >  2 *  100khz to 25Mhz  DSS  frequency genorators      
> >  a spartan 3  xc3s400 fpga (75% avalable for user ip)    
> >  64MB ddr video ram      
> >  dvi-i video (both digital and analog)    
> >  composite video output     
> >  a 32 dio fpga port / expansion bus ( allowing for 50Mhz +  
> signal    
> > clocking )    
> >  a lower speed  dio and analog expansion port    
> >     
> >  on a 160mm * 100mm 4 layer pcb      
> >     
> >  if verification of the design goes ok then the prototypes 
should  
> be    
> > under construction in the next 3 months , and allowing another 2  
> to    
> > 3 months for the software port and ip core writing before the  
> design    
> > is totaly finalised     
> >     
> > anyone interested in getting involved in the development ether  
> email    
> > me at the email on the schematics , or  in irc chat on  
> freenode.net    
> > channel #openhardware     
> >     
> > (sorry that this is slightly off topic)    
> >     
> > Dave  (achiestdragon) 
> > 
> 
 






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