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[ts-7000] Re: new GNU openhardware ep9302 based SBC

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Subject: [ts-7000] Re: new GNU openhardware ep9302 based SBC
From: "Jesse Off" <>
Date: Sat, 06 May 2006 00:38:41 -0000
Interesting board.  Did you use all GNU/GPL software for schematic
capture and board layout also? 

BTW, Your LEDs are reversed biased on the schematic.  Curious as to
why you put a diode inbetween 5V and the CF VCC like we did on the
TS-7200? 

I definitely look forward to seeing this hardware proven and any
subsequent software/hardware cores created.  Those will be GPL too
right?  We may manufacture this ourself (or quote it for custom
designs) if the BOM and manufacturing costs aren't too high. 

We hadn't seen that DVI chip before.  We may actually have a use for
that chip out here in the future. 

//Jesse Off

--- In  "pickanameanditstakensoihavethis"
<> wrote:
>
> hi          
> well now the first step is done          
> the initial schematics are now complete         
>          
> http://www.whipy.demon.co.uk/geep-sch.pdf        
>         
> and the coresponding pcb artwork         
>         
> http://www.whipy.demon.co.uk/geep.pdf        
>         
> we now would like some to look it over and let us know if there
are         
> any potential problems before we commit to having the prototype
pcbs  
> made          
>         
> the geep is a open source  GNU GPL licenced  unit         
>         
> it offers         
>  ep9302  200Mhz arm cpu        
>  up to 256MB of sdram      
>  512MB of on board flash       
>  T10/100 ethernet    
>  2 * usb    
>  rs232    
>  ps/2   
>  ac97 audio codec   
>  ide   
>  compact flash   
>  2 *  100khz to 25Mhz  DSS  frequency genorators    
>  a spartan 3  xc3s400 fpga (75% avalable for user ip)  
>  64MB ddr video ram    
>  dvi-i video (both digital and analog)  
>  composite video output   
>  a 32 dio fpga port / expansion bus ( allowing for 50Mhz +
signal  
> clocking )  
>  a lower speed  dio and analog expansion port  
>   
>  on a 160mm * 100mm 4 layer pcb    
>   
>  if verification of the design goes ok then the prototypes should
be  
> under construction in the next 3 months , and allowing another 2
to  
> 3 months for the software port and ip core writing before the
design  
> is totaly finalised   
>   
> anyone interested in getting involved in the development ether
email  
> me at the email on the schematics , or  in irc chat on
freenode.net  
> channel #openhardware   
>   
> (sorry that this is slightly off topic)  
>   
> Dave  (achiestdragon)
>






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