--- In shane warne <>
wrote:
>
> how is power on reset different from manual reset?is it that
the some chips are not affected by manual reset and some are??
>
> also how can one work(play) with the CSn[0,1,2,3,6,7] pins, which
controller controls them?
>
> what about the CSn[4,5]?? aren't they on the board? if yes, is
there any specific reason for naming the pins so.
>
hi
the CSn pins are provided by the ep9302 there provided as an
address decode from the upper portion of the address lines
there mapping is as follows
Fxxx xxxx SDRAM CHIP 4
Exxx xxxx SDRAM CHIP 3
Dxxx xxxx SDRAM CHIP 2
Cxxx xxxx SDRAM CHIP 1
Bxxx xxxx --------DNU--------
Axxx xxxx --------DNU--------
9xxx xxxx --------DNU--------
8xxx xxxx on chip i/o space
7xxx xxxx CSn7
6xxx xxxx CSn6
5xxx xxxx --------DNU-------
4xxx xxxx --------DNU-------
3xxx xxxx CSn3
2xxx xxxx CSn2
1xxx xxxx CSn1
0xxx xxxx CSn0
each block addressed is a 256MB address space althugh only 64Mb is
accessable in each
there provided so it is easy to interface a couple of memory/io
devices without the need for external logic
the missing ones are reserved and not to be used as is there address
space
note that CSn0 may be diferent from above depending on the boot
memory device and configuration beeing used
the power on reset differs from the normal reset in that a normal
reset does not reset some parts of the cpu like the pll settings
a good explanation of the exact opperation is given in the ep9301
user guide (on cirrus logics site )
its worth reading :) even if it seems to miss a lot of what should
be there
Dave
> --Warney
>
>
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