Hi Jesse,
Regarding what you mentioned about what is released to the public
domain, etc. and in relation to the ADC driver I have developed, is
it at all possible that the interrupt source from the add-on ADC
does go somewhere so that the CPU get be interrupted? I haven't had
a chance to examine the actual board to well, but the schematics
show that the int output doesn't go anywhere. Just hoping (wishful
thinking) that that might not be the case??
Cheers
Phil
--- In "Jesse Off" <> wrote:
>
> --- In anand bhavnani <ajbanand@> wrote:
> >
> > As u have mentioned the processor handles flash through the cpld
and
> additionally cpld perfoms several other functions.
> >
> > so can i assume that the cpld is on the board primarily because
the
> processor in itself is not having a controller (like uart
> controller,VEC. INT. ,...etc) that could have effectively
interfaced
> with the flash and hence the need for cpld arose.
>
> no. IMHO, having dedicated "NAND flash controller" pins
implemented
> on a CPU would only serve to waste pin real-estate on the CPU
package.
> Interfacing NAND flash chips isn't rocket science (Its
implemented in
> just a 72-macrocell CPLD after-all) The CPLD already is needed and
> cost-justified for other duties it has on the board, so we really
got
> NAND support for "free". If it were on the Cirrus CPU, we'd be
paying
> Cirrus for that (imaginary) NAND interface on every TS-7xxx board
> whether or not we actually even had a NAND chip in the design.
When
> it comes down to it, the SMC bus is perfectly fine for NAND flash
chips.
>
> Almost all of the boards we design have a CPLD (or an FPGA such as
the
> TS-7260 or TS-7300) on them and only the TS-7250 and 7260 have NAND
> flash chips. It gives much design flexibility and helps to keep
the
> number of discrete chips low. We also can custom program the CPLD
for
> customers with special needs without having to do a (more
expensive)
> board redesign. (e.g. DIO pins that do quadrature or PWM instead of
> just regular in/out)
>
> Also, there is subtle "secret sauce" in the CPLD code that deters a
> casual Joe Engineer from using the published schematics to
> remanufacture or create new CPLD code for themselves. Or at least
one
> that will work reliably. Likely, a wrong CPLD load would even
cause
> boards to self-destruct in very unique ways. TS reserves this CPLD
> code, the PCB gerbers, and full schematic details for customers who
> license the design while releasing most of the rest to the public
domain.
>
> Usually, getting sound is best approached with a $10 USB sound
dongle.
> Using the CPU to simultaneously sample the ADC at 10-40 KHz, feed
a
> raw DAC chip and run Linux or any other type of processing is just
> asking for trouble. Such a job is cake for a DSP, but a general
> purpose CPU running an operating system really likes more hardware
> help than the typical raw ADC/DAC provides. (for instance, FIFO's
and
> a sampling clock generator)
>
> //Jesse Off
>
>
> >
> > also please suggest a DAC that i may use to provide the sound
> support to the board considering the fact that i am using MAX197 12
> bit ADC.
> >
> > thanks,
> > //anand.
> >
>
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