The address and data pins are shared between the SMC bus and the SDRAM
bus. IIRC, the only thing thats not buffered on that design was the
SDRAM. This is mostly due to safety and reliability rather than
loading-- if something starts misbehaving on the buffered side of
those pins, the SDRAM and the CPU should remain unaffected. The 245's
serve as a "firewall" of sorts for the much more critical, sensitive
and higher speed SDRAM. Those tracks were also kept as short as
possible for best possible signal integrity and highest potential
margins. The buffered side snakes all over to the PC104 bus, RTC,
ADC, CF, CPLD, and flash so its potential for failure is much higher.
If something on the PC104 bus jams the data bus, it doesn't effect
the CPU <-> SDRAM interface and the board has the option to continue
running.
//Jesse Off
> The one thing I don't understand is; why is the flash connected to the
> buffered side of the data bus? and not directly to the controller. I
don't
> think the capacitance on the bus is more than the 50pF recommended
with only
> two sdrams. Maybe they wanted to isolate the flash from the data bus
so both
> buses can operate independently? Maybe routing was easier?
>
> -Curtis.
>
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