The CPLD is used to control the NAND flash. By setting registers in the CPLD
you can set the ALE and CLE control lines for the flash. Another register on
the CPLD tells you if the NAND is busy or not. (its busy when its writing or
erasing pages, or preparing a page to read)
The CPLD also converts the SRAM bus control signals to RD, WR, and CS signals
for flash.
The CPLD does more than just NAND flash management. It also:
- handles control signals on the PC104 bus,
- has a watchdog timer,
- lets you read the jumper settings,
- does some stuff with UART2
- handles the rest button
- handles the voltage supervisor to delay bringing the EP9302 out of
reset
till the power has settled.
- interfaces to the Real time clock
- controls the EEPROM chip select, (e.g. to turn it off after booting)
The one thing I don't understand is; why is the flash connected to the
buffered side of the data bus? and not directly to the controller. I don't
think the capacitance on the bus is more than the 50pF recommended with only
two sdrams. Maybe they wanted to isolate the flash from the data bus so both
buses can operate independently? Maybe routing was easier?
-Curtis.
On February 9, 2006 10:41 am, anand bhavnani wrote:
> Friends,
>
> the 7250 has Xilinx 9572 CPLD on the board. the flash is connected to it.
> can please someone let me know why is it so..
> what is the purpose of cpld..
> also can i do without the cpld, or replace it with some other..
>
> also what equipment(for downloading, specifications) would i need for the
cpld..
>
> good bye,
>
> //anand.
>
>
> "Stay HUNGRY. Stay FOOLISH." Steve Jobs
>
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