Thanks for the quick reply.
We've been using Altera MAX-3000A class chips, typically the EMP3064.
We designed several boards for customers around the same basic decode
logic. All use one or more "target" chips that have a few registers
mapped into I/O space. None of the boards use the OSC line.
I wrote some low-level "sanity" diagnostic tests for each board.
Typical would be to just write some values to R/W registers on the
peripheral board then read them back, and compare to the written
values. This is just the first level of tests that each board must pass.
I tried two different peripheral boards with the TS-7200. Each had a
(different) USB peripheral/slave chip that used an indexed register
set. One used 16-bit read/writes, the other 8-bit. The test was: write
the index, write the value, write the index, read the value. Compare.
I would get some results that were close (such as one of two bytes
read back were correct, the other garbage or the first byte repeated).
Sometimes it would fail 5 times out of 100 tries.
Could there be some other timing issues? Or something like that I
could look for? I don't have the leeway to change the hardware at this
point, but I wrote all the drivers and can mess with software to my
heart's content.
Thanks,
Frank
--- In "Jesse Off" <> wrote:
>
> --- In "Frank Pagliughi" <>
wrote:
> >
> > Actually, it seems that PC/104 signals from many controller boards has
> > gone to 3.3V even on x86 motherboards - especially those using the
> > newer embedded processors, such as the AMD SC520 and similar.
> > Normally, the power lines, VCC, are at 5V, but signals generated by
> > the controller, such as RD & WR, only drive high to 3.3V. All inputs
> > to the motherboard would be 5V tolerant.
> >
> > This has created some problems with older peripheral boards,
> > especially those using discrete decode logic. A little ringing on the
> > control lines (especially /IOR & /IOW) create some strange behavior.
> > Usually a small series resistor on the line coming into the board
> > would fix the problem - assuming the peripheral board was of your own
> > design and could be changed. I believe PC/104 was originally spec'd to
> > have RC termination on the lines, anyway (??)
>
> No, PC/104 doesn't include this, though we have seen many custom
> boards use this type of "band-aid" RC termination solution to deal
> with large stacks of boards on the PC/104 bus. The TS-7xxx boards use
> controlled slew rate to mitigate ringing as much as possible on the
> strobe signals.
>
> You are also correct in that all signals driven by the CPU are 3.3V.
> The original PC104/ISA spec was indeed 5V but they were also specified
> as TTL signaling. TTL signaling at 5V is 100% compatible with 3.3V
> CMOS logic since 3.3V is above the 5V TTL input threshold of 2.4V and
> output threshold of 2.8V.
>
> A lot of people take advantage of the fact that the TS-7xxx boards
> only put 3.3V on the PC104 bus. If you intend to control what other
> boards get plugged in to the PC104 bus, you don't have to 5V harden
> your custom board. (saving costs, board area, reducing board
> complexity and avoiding extra propagation delays from a buffer chip)
>
> >
> > We never had any problems with peripheral boards that used a CPLD for
> > decode, even when the motherboard was sourcing 3.3V on the control
> > lines. I believe all or CPLDs were running at 3.3V with 5V tolerant
> > inputs, anyway.
>
> It seems 5V tolerance isn't as marketable a feature anymore to IC
> manufacturers and newer CPLDs such as the MAXII family from Altera
> aren't 5V tolerant. The Xilinx CPLDs we have traditionally used all
> are 5V tolerant. Our designs have typically used LVC245 chips to
> buffer the non 5V parts from the 5V parts.
>
> >
> > That said... we were never able to get any of our PC/104 periperal
> > boards running reliably with a TS-7200, though admittedly, we didn't
> > put much time into finding out why. We may look to revisit this soon,
> > since we have a number of upcoming applications that would go well
> > with the board.
> >
> > Any insight would be appreciated.
>
> Every board we've tried hasn't had a problem electrically-- what we've
> found however is a lot of software drivers in OS's without a ISA bus
> abstraction layer (Linux, most RTOS's, etc..) needed some changes.
> However, one thing we know that may cause a problem is if your board
> uses the PC/104 14.318Mhz OSC pin, this clock has somewhat high jitter
> on the TS-7xxx. Normally this isn't a problem, but if you're using
> that line in a DLL or PLL to synthesize another frequency, you may run
> into problems with the DLL/PLL acheiving lock. There is a register
> that you can poke on the TS-7xxx to send a 0 jitter clock, but you
> will get 14.7456Mhz instead of 14.318Mhz.
>
> //Jesse Off
>
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