> thanks for the info
> i had 99% finished the design and had opted to use level shifters
> to ensure compatibility but may change back as it gives me a few
> more options
>
> i am working on a fpga board using a cyclone2 (ep2c20q240c8) fpga
Great! Keep in mind that although all signals on the PC/104 bus are
only driven to 3.3V by the CPU, the data bus (and only the data bus)
will be driven to 5V levels by the CompactFlash card (TS-7200 only),
the battery backed RTC, and the MAX197 ADC optional component. So you
may want to put buffers on just the data bus.
Also, I notice you route the OSC pin into the FPGA. The jitter on
that pin will more than likely prevent it from being able to be used
to feed a cyclone2 altpll. You may want to consider putting a
dedicated 25Mhz or 33Mhz crystal oscillator onboard.
We have used the cyclone2 FPGA and have built a small (25 LUT) CPU
FPGA loader core on a Altera MAXII CPLD (Implemented in Verilog
w/wishbone bus). We have also written the software on the TS-7xxx
that allows us to use this core to load an Altera .rbf file on stdin
to an Altera FPGA. Reconfiguring/loading a 2C8 FPGA with this
software/hardware takes about 0.2 seconds on the EP9302 processor. We
had to design similar hardware/software for Xilinx-- which is on the
TS-7KV board. If this may be useful to you, let me know.
//Jesse Off
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