Re: [ts-7000] Re: Avoiding task preemption by Linux kernel

[mike ingle <>]

Hi Dorian,

Your approach should work. I had a bad experience using the TS-7300, which had the FPGA connected indirectly to the ARM processor via a CPLD, and full timing specs were not available.  Others had better results, and eventually I managed error free (at least in 100M read/write cycle testing).  Your board appears to have an open FPGA project, and is a simpler connection to the processor, so you should not have problems communicating with the FPGA.  One issue (I haven't looked at the details of your board) may be SD card support,  Technologics tends to use proprietary FPGA code to interface SD cards.  On the TS-7300 I had to forego all Techonologics FPGA modules, and only use the FPGA for my own purposes.  I don't know if you can include technolgics modules in your own design,  or if you even need them.  To the good, you will probably have a simple skeleton project avail to you which will allow register read write over the spi to the processor.  I have used other boards where the FPGA to processor support/ example project was good enough that I could complete the project very quickly and everything went together well.  That was not my experience with the ts7300.  Another option is to use technologics engineers to modify the fpga IP to your purposes.

Good luck with your project,

Mike

On Aug 16, 2011, at 7:21 AM, tourindorian wrote:

 

Thanks for all your ideas, it will be very helpful.

Actually, the SPI transaction cannot be interrupted during 20ms. I'll try do develop a kind of Linux kernel to handle that process.

What if the FPGA continuously (16 bits each 80µs) communicated with the ADC using an external SPI bus and stored the data in a buffer that could be asynchronously read by the processor in 'burst' mode? It would require to modify the FPGA code, but I guess that's not too complicated..?

Dorian.

--- In ts-7000%40yahoogroups.com, mike ingle <> wrote:
>
> If you are up to it, then a transaction approach where the kernel talks to the fpga over spi to a queue, and a state machine in the fpga handles the time critical code should work well.
>
> XMOS makes several nice multi-threaded processors, which handle this kind of application very cleanly. Inexpensive too. I am using one where I have a state machine on a 20us cycle time which handles all SPI transactions and maintains the system state in one thread, and other threads handling communications...
>
> Regards Mike
> On Aug 12, 2011, at 6:04 AM, tourindorian wrote:
>
> > Hi,
> >
> > I'm developing an application (C code) on the TS7550 board, using Linux 2.6. I got an issue trying to use continuously the SPI bus for 20ms.
> > Every 10ms, the communication is interrupted during about 0.5ms. I guess the Kernel scheduler interrupts the process.
> >
> > Do you have any idea to fix it? Could I change the tick rate of the scheduler so that it is about 50 or 100ms instead of 10ms? Could I prevent the Kernel from preempting the task during that critical section?
> >
> > Any idea would be useful :-)
> >
> > Many thanks,
> >
> > Dorian.
> >
> >
>

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