Thanks for all your ideas, it will be very helpful.
Actually, the SPI transaction cannot be interrupted during 20ms. I'll try do
develop a kind of Linux kernel to handle that process.
What if the FPGA continuously (16 bits each 80µs) communicated with the ADC
using an external SPI bus and stored the data in a buffer that could be
asynchronously read by the processor in 'burst' mode? It would require to
modify the FPGA code, but I guess that's not too complicated..?
Dorian.
--- In mike ingle <> wrote:
>
> If you are up to it, then a transaction approach where the kernel talks to
> the fpga over spi to a queue, and a state machine in the fpga handles the
> time critical code should work well.
>
> XMOS makes several nice multi-threaded processors, which handle this kind of
> application very cleanly. Inexpensive too. I am using one where I have a
> state machine on a 20us cycle time which handles all SPI transactions and
> maintains the system state in one thread, and other threads handling
> communications...
>
> Regards Mike
> On Aug 12, 2011, at 6:04 AM, tourindorian wrote:
>
> > Hi,
> >
> > I'm developing an application (C code) on the TS7550 board, using Linux
> > 2.6. I got an issue trying to use continuously the SPI bus for 20ms.
> > Every 10ms, the communication is interrupted during about 0.5ms. I guess
> > the Kernel scheduler interrupts the process.
> >
> > Do you have any idea to fix it? Could I change the tick rate of the
> > scheduler so that it is about 50 or 100ms instead of 10ms? Could I prevent
> > the Kernel from preempting the task during that critical section?
> >
> > Any idea would be useful :-)
> >
> > Many thanks,
> >
> > Dorian.
> >
> >
>
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