As of today there is a dirth of information about the I/O header on the
8390. Below is my attempt to get at the first 4 INs and first 5 OUTs on
the header. This was gleaned from the ts4800ctl utility and then finding
the bit mapping empirically. Maybe this will be useful to someone else,
at least until the user manual arrives.
Regards,
Jim Ham
<----->
//directio.h
// remapped bits used internally
// output bits
#define OutputEna (1<<0)
#define WarnALARM (1<<1)
#define LimitALARM (1<<2)
#define OutSpare1 (1<<3)
#define OutSpare2 (1<<4)
// bits in input word
#define NEWROLLRQSTINBIT (1<<0)
#define ALARMRESETINBIT (1<<1)
#define INSPARE1BIT (1<<2)
#define INSPARE2BIT (1<<3)
void DirectIOInit(void) ;
int ServiceNativeButtons( void) ;
int SendBinOut( int IOshadow ) ;
<--------->
<--------->
//directio.c
#include <sys/mman.h>
#include "directio.h"
#define TS_REG_BASE (0xb0010000)
#define TS_IN_REG (0x20/2)
#define TS_OUT_REG (0x22/2)
#define TS_DIR_REG (0x24/2)
#define TS_NEXT_OFFSET (0x08/2)
/*
bit numbers in a 56 bit word from 8390 hardware.
Map bits 32-47 to bits 16-31 so will fit in long.
This only works because (so far) we are not using any bits
in the range 16-31!
*/
/*
bit map for inputs and outputs:
registers are 64 bits!
input:
0 (new roll) bit 8 0x00 0000 0000 0100
1 (alarm ack) bit 9 0x00 0000 0000 0200
2 (spare1) bit 41 0x00 0200 0000 0000
3 (spare2) bit 3 0x00 0000 0000 0008
output:
ena bit 0 0x00 0000 0000 0001
0 (warning) bit 1 0x00 0000 0000 0002
1 (limit) bit 2 0x00 0000 0000 0004
2 (spare1) bit 40 0x00 0100 0000 0000
3 (spare2) bit 39 0x00 0080 0000 0000
*/
#define OUT_0 (0)
#define OUT_1 (1)
#define OUT_2 (2)
#define OUT_3 (40-16)
#define OUT_4 (39-16)
#define IN_0 (8)
#define IN_1 (9)
#define IN_2 (41-16)
#define IN_3 (3)
#define MAP_OutputEna ((long)1<<OUT_0)
#define MAP_WarnALARM ((long)1<<OUT_1)
#define MAP_LimitALARM ((long)1<<OUT_2)
#define MAP_OutSpare1 ((long)1<<OUT_3)
#define MAP_OutSpare2 ((long)1<<OUT_4)
#define MAP_NewRoll ((long)1<<IN_0)
#define MAP_AlarmAck ((long)1<<IN_1)
#define MAP_InSpare1 ((long)1<<IN_2)
#define MAP_InSpare2 ((long)1<<IN_3)
volatile unsigned short * ts_map ; // buttons image appears here
/************************************************************************
map the binary input/output registers to user space
***********************************************************************/
void DirectIOInit(void) {
PortImage = 0 ;
int devmem ;
devmem = open("/dev/mem", O_RDWR|O_SYNC);
if ( devmem < 0 ) {
perror( "open in InitIO" ) ;
exit (EXIT_FAILURE) ;
}
ts_map = (unsigned short *) mmap(0, 4096,
PROT_READ | PROT_WRITE,
MAP_SHARED, devmem, TS_REG_BASE);
if ( ts_map == MAP_FAILED ) {
perror ("mmap in InitIO" ) ;
exit (EXIT_FAILURE ) ;
}
// set the direction register
ts_map[TS_DIR_REG] =
(MAP_OutputEna |
MAP_WarnALARM | MAP_LimitALARM | MAP_OutSpare1 | MAP_OutSpare2)
& 0xffff ;
ts_map[TS_DIR_REG + (TS_NEXT_OFFSET*2)] =
((MAP_OutputEna |
MAP_WarnALARM | MAP_LimitALARM | MAP_OutSpare1 |
MAP_OutSpare2)>>16) & 0xffff
;
IOshadow = 0 ;
SendBinOut( ) ;// shut off all, sets ENA
}
/*
***************************************************************************
pick up and remap button inputs from the 8390 hardware
****************************************************************************
*/
int ServiceNativeButtons( void ) {
long sntmp ;
int short PortImage ;
// note that we are only looking at bits 0-15 and 32-47
sntmp = (long)ts_map[TS_IN_REG] | ((long)ts_map[TS_IN_REG +
(TS_NEXT_OFFSET*2)]<<16
) ;
// take a look to see if a button has been pushed...
PortImage = 0 ;
if ( !(sntmp & MAP_NewRoll)) PortImage |= NEWROLLRQSTINBIT ;
if ( !(sntmp & MAP_AlarmAck)) PortImage |= ALARMRESETINBIT ;
if ( !(sntmp & MAP_InSpare1)) PortImage |= INSPARE1BIT ;
if ( !(sntmp & MAP_InSpare2)) PortImage |= INSPARE2BIT ;
return PortImage ;
}
/**************************************************************************
Remap and send bits to the 8390 hardware
***************************************************************************/
int SendBinOut( int IOshadow ) {
long sbtmp ;
sbtmp = 0 ;
if ( IOshadow & OutputEna ) sbtmp |= MAP_OutputEna ;
if ( IOshadow & WarnALARM ) sbtmp |= MAP_WarnALARM ;
if ( IOshadow & LimitALARM ) sbtmp |= MAP_LimitALARM ;
if ( IOshadow & OutSpare1 ) sbtmp |= MAP_OutSpare1 ;
if ( IOshadow & OutSpare2 ) sbtmp |= MAP_OutSpare2 ;
// note that we are only addressing bits 0-16 and 32-47
ts_map[TS_OUT_REG] = sbtmp & 0xffff ;
ts_map[TS_OUT_REG + (TS_NEXT_OFFSET*2)] = (sbtmp >> 16 ) & 0xffff ;
return 0 ;
}
<-------------->
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