> While we open up most of the FPGA, we do not release the bootloader,
>this is proprietary information. We can release the source code by
>making sure any loads of the FPGA are loaded only in the SRAM and not
>the flash cells. This makes sure the bootrom stays in place and is
>kept confidential. The only caveat is that the FPGA must be reloaded
>every boot cycle, but this only adds a second or two to the total time.
I don't understand is if your loader is inside the fpga or not? I mean, if i
recompile the verilog and reprogram the fpga with the new bitstream, will the
board work like before or must i use a different loader (u-boot or similar) ?
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