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Re: [ts-7000] Re: Sub 10ms delay on TS-7552 (Cavium cpu)

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Subject: Re: [ts-7000] Re: Sub 10ms delay on TS-7552 (Cavium cpu)
From: Michael Schmidt <>
Date: Tue, 13 Jul 2010 10:27:54 -0700
On 7/13/2010 7:00 AM, Jean-Francois wrote:
>
>
>
> I just confirmed now why they shouldn't have gone this way and going
> everything through the CPLD...
>
> I was struggling to make CAN communication run smoothly. In our
> application, we have nearly 150 CAN messages on the bus every 500ms
> (TS7552 sends 26 and receives 121). I had problems because the other
> controllers on the network were regularly reporting communication
> timeouts. I started to time everything and found that sometimes
> buslock() calls can stall for several hundreds milliseconds... All
> hardware interfaces are going through the CPLD and use buslock(). For a
> test, I copied a file to the SDcard while our software is running and it
> made CAN communication completely erratic. Thats really not good...
> Design issue?

It's a limitation of the Cavium CPU, which uses SPI for its peripheral 
bus.  Since access to this bus is not atomic a locking mechanism is 
required.  The SD card driver in particular bursts something like 256 
reads or writes at a time in between preemption points for efficiency. 
You might want to look at the source code for sdctl to tweak the 
preemption points for a lower burst length and for canctl to try to send 
more packets every time it gets the bus.  (The CAN controller has a 128 
packet Rx FIFO but only has 1 packet pending to Tx at a time)

  ______   Best Regards,
|__  __/                  Michael Schmidt
    ||                   Software Engineer
    ||echnologic Systems (EmbeddedARM.com)
    || (480)        16525 East Laser Drive
    |/ 837-5200   Fountain Hills, AZ 85268
        http://oz.embeddedarm.com/~michael


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