--- In "bburtan" <> wrote:
>
> >
> > I don't see where the datafile has *any* channel info. Why do you
> > think it should?
>
> The ADC24 has to read blocks of 4 channels and you can't tell it to read only
> one channel or a specific channel so the data must have the channel source ID
> available. Even if you set the ADCCFG NUMCHAN to 0, you're always getting 4
> channels in the FIFO (two from Chip 0 and two from Chip 1).
>
OK, I thought you were using the example code 'as-is'...
> But, I finally figured it out by decyphering the tsadc.lib file. I had been
> looking at bits 14-12 of ADCFIFO (BASE+0A) because the description says
> "CURNUMCHAN current number of channel for the data read". Apparently that's
> not the specific channel. Bit 15 is indeed ADCCHIP. So I'm guessing that
> bits 14-12 are really which block of channels the data belongs to. Kinda
> useless, IMHO.
>
> Ultimately, looking at bits 5-1 of ADCSTAT (BASE+08) will give you the actual
> channel in the current head of the FIFO. Of course you need to look at this
> value before you look at ADCFIFO (BASE+0A) because as soon as you look at
> ADCFIFO, it clicks to the next sample.
>
> Also, the ADC data is in 2's compliment format even if you've told the ADCCFG
> range to be 0-5 volts so you need to convert the data to get a real voltage
> value out of it.
>
> Now my next issue is determining what the actual timing is. The docs say
> that the conversion time is 1 usec. Is that per channel? Per chip i.e. per
> two channels? Per block of four channels?
The AD7266 chip (at 3V supply) needs about 0.6 usec per conversion, and one
conversion could be one differential, or two single ended. You still need to
add settling time, etc, to get throughput estimates. And since there are (2)
AD7266 chips on the board, I presume the FPGA can operate them in parallel,
giving you (2) DE conversions or (4) SE conversions every 0.6 usec.
Are the chips powered at 3V or 5V? It makes a difference in the response and
speed of the chip (1.5 vs 2 MSPS, THD, etc.). I guess you've already found:
http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7266/products/product.html
The datasheet is a great reference. Although it doesn't tell you the details
of how the FPGA talks to the A/D chips, it may be a help when reviewing the
tsadc.lib shell programs for operational details and designing your input
signal conditioning.
regards, ......... Charlie
>
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