Michael,
--- In Michael Schmidt <> wrote:
> All the bitstreams we provide update the internal RAM inside the part,
> and must be loaded on every boot.
>
> I was not involved in the development but I understand from talking to
> the engineer that we ran into some issues during development of
> load_ts7350 whereby loading a bitstream into flash from a user-space
> program makes it very easy to brick the board.
Thank you very much for your valuable reply.
I'd suggest to update the documentation in order to make this point a little
bit more clear.
I tell you so because I understand you work with people at TS. ;-)
> It is not possible to "read back" the bitstream from the FPGA. This is
> a security feature and part of the design of the FPGA which we have no
> control over. The best way to determine if the new bitstream is loaded
> is to have a unique register value (e.g. revision number) somewhat that
> you can read. However this is dependant on whoever updates the HDL code
> to do this.
Any idea if something similar is implemented for TS-7350 bitstreams? Could you
suggest a better place to ask?
Regards,
Andrea
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