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Hi Michael, Thank you for your input! We decided to keep very tight control over the list of contributors to the wiki just to keep "noise" out of it. But I will add the information you have provided once it's clear to myself. First of all regarding the PCI pins, I know that in theory it's just the extra clamp diode, but those pins, when checked in EPIC Device Editor, seem to also be arrange a lot better for the idea of a bus. Right now there is no way you can have an FPGA design to be located close to PCI pins. You have 2 pins on the top edge, 7 pins on the bottom edge and the rest on the left edge. Even the simplest address decoding requires signals to cross the whole matrix of slices. I'm working on a design that handles 160MB/s of data (16-bit, 80MHz ADC) and the PCI works at 60MHz. It's quite at the very limit that the FPGA can do with the current connections. My design works, but with extra registers to insure the delay doesn't exceed the high speed clock period. Just for fun, I have tried the same Verilog file with a .prf file to match an ideal PCI pins mapping. The speed difference wasn't that insignifiant because all PCI related stuff was strictly in the bottom quadrant of the FPGA. But what's done is done and we have to live with it! I'm glad that I have found a way of getting it working. As for the partition table thing, Alex has initially found out that kernels larger than 3MB can't be loaded by the MBR. And I hate the idea of initrd. So we started playing with the partition tables of both the NAND and the SD card and learned theor problems the hard way. Practically not all the space was used for the kernel and the initrd partition. At a given moment new MBRs have been uploaded on the FTP server and a binary comparision showed that just the partition tables have been modified. So we started playing with them. Right now we use 4Mb for kernel, I have dropped initrd completely, and we no longer have MBR related issues. The other problem, with the correct ARM Machine ID for having proper support in mainline kernel, I have done it by looking into the binary of the MBR and searching for the value announced by a debug kernel that refused to load. And I have corrected it with a hex editor. But now, with the source code of the partition table, we will put it on the wiki and, if you agree, also put there a binary version with correct machine ID. Many thanks, Catalin __._,_.___
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