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Welcome to the club! I have decided to "attack" the FPGA programming issue myself once I clearly saw that TS is not going to release any bitstream loader, as they initially announced. Right now I have implemented almost completely what I actually need, banged myself against the wall several times during FPGA development, but it will almost completely end up in a wiki I'm prepping with Alex Clouter, the TS-7800 mainline kernel maintainer. I will stop myself, most probably, to what I have already implemented in my FPGA structure, at least for the moment. That means really minimum support for what is needed to get going my project, but it's a starting point a lot more useful that just a schematic and the TS provided info. From my point of view, TS could have provided a lot more info or even a simplified FPGA design to be released on OpenCores.org, as they did with one of their previous boards. But as they probably put some serious work into the current bitstream, maybe even having some royalties to pay for stuff like SDHC, I really don't blame them. Having the schematic and whatever info they provide, after all, I was able to get it going. Also, these days, I no longer need to use UrJTAG. Instead I have looked into the SVF file and implemented a direct bitstream loader. It's a lot faster and the bitstream is embedded in the application, as binary, so a lot more difficult to reverse engineer. After all, I need to protect to some degree my work. Catalin __._,_.___
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