Hi --
--- In Jim Jackson <> wrote:
> On Wed, 21 Jan 2009, Val Schmidt wrote:
>
> > Wow!
> >
> > I certainly was not operating the CPU at 2.5 Mhz!
> >
> > In this thread:
> > http://tech.groups.yahoo.com/group/ts-7000/message/2510
> > there is discussion of your "cctl" code and it's ability to
"bypass PLL1 and
> > PLL2". I'm sorry, I'm new to all of this. Could you explain what
PLL1 and
> > PLL2 provide and what are the implications of bypassing them?
>
> PLL1 & 2 are pieces of hardware in the copy for generating stable clock
> signals for various parts of the chip, CPU, Memory, various bus'es etc.
> There is a lot of info on this in the EP9301 User's Guide
>
> http://www. embeddedarm.com/downloads/Components/EP9301_User_Guide.pdf
>
> in Chapter 4 - System Controller.
Also, Matthieu has ep93xx cpufreq and pm patches in his 2.6.27.4
patchset that are interesting reading. Look in the files section of
the news group. (But note the ep9302 constants, which you probably
want, are commented out in favor of the ep9301 constants).
Watch the nF bit too. If it is inadvertently cleared (as redboot
does), the CPU core will run from HCLK rather than FCLK, and you'll
wonder what's going on ....
If you really want to be on the cutting edge, support for
suspend-to-ram is currently being worked on & moved into upstream
kernel, mostly for the s3c family of chip (courtesy Openmoko). Some
generic support is going in too, like teaching the VIC about suspend &
resume. I haven't seen any ep93xx stuff, but there are good templates
to follow now if you feel ambitious. I don't know if there are any
hardware issues that would keep TS boards from doing STR.
regards, ....... Charlie
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