On Wed, 21 Jan 2009, Val Schmidt wrote:
> Wow!
>
> I certainly was not operating the CPU at 2.5 Mhz!
>
> In this thread:
> http://tech.groups.yahoo.com/group/ts-7000/message/2510
> there is discussion of your "cctl" code and it's ability to "bypass PLL1 and
> PLL2". I'm sorry, I'm new to all of this. Could you explain what PLL1 and
> PLL2 provide and what are the implications of bypassing them?
PLL1 & 2 are pieces of hardware in the copy for generating stable clock
signals for various parts of the chip, CPU, Memory, various bus'es etc.
There is a lot of info on this in the EP9301 User's Guide
http://www. embeddedarm.com/downloads/Components/EP9301_User_Guide.pdf
in Chapter 4 - System Controller.
In conjunction with that description, you can"experiment" with different
settings of some of the system registers. Bit settings in system registers
ClkSet1 and ClkSet2 control what frequency clocks the PLL's generate, and
there is a bit setting that by-passes the PLL forcing the chip to run of
the extrnal oscillator, which runs at a freq. of 14.7MHz if memory serves.
I've not actual run with the PLL's bypassed (or if I did, I've not made any
notes of results).
I would urge you to read the full relevant bits of section 4 in the EP9301
manual before experimenting, especially section "4.1.5.2.1 Bus Clock
Generation" where the limitations of the clock settings are detailed.
The FCLK is the processor clock, the HCLK is the AHB bus clock (MMU, Cache,
DMA controller and RAM), and the PCLK is the APB bus clock (lower speed
peripherals).
>
> Also in this thread is an anecdotal comment that lowering the HCLK (high
> speed clock?) was found to reduce the power consumption greatly after
> securing the PHY. Again, I'm not sure what the implications of lowering the
> HCLK might be. (or how to do it yet)
>
> -Val
>
> On Jan 21, 2009, at 4:36 AM, Jim Jackson wrote:
>
>>
>>
>> On Mon, 19 Jan 2009, Val Schmidt wrote:
>>
>>> Hi,
>>>
>>> I am the proud new owner of a ts-7260. The documentation describes an
>>> operating mode in which the unit consumes on order of 0.25 W. Would
>>> anyone have a list of all the things one has to turn off to reach this
>>> level?
>>>
>>> In my own first-go, I was able to reduce power from about 1.5W to .83W
>>> by operating at the minimum cpu speed and powering down eth0 and the
>>> phy and turning off the USB. But I'm not sure where to go from there.
>>
>> What do you believe the min cpu speed is? I've operated the TS7200 board
>> with CPU clocked at aprox 2.5MHz. The min cpu clock rate for ethernet to
>> work is 40MHz.
>>
>> Even on the ts7200 (which, unlike the ts7260, is not designed for very low
>> power) I got as low as 0.8W with a very low cpu clock and the ether phy
>> turned off. I'd have thought that the 7260 in the same sate would have use
>> quite a bit less power.
>>
>> Jim
>> ----------------------------------------------------------
>> HomePage: http://www.comp.leeds.ac.uk/jj
>> TS7200 Page: http://www.comp.leeds.ac.uk/jj/linux/arm-sbc.html
>>
>>
>
> ------------------------------------------------------
> Val Schmidt
> CCOM/JHC
> University of New Hampshire
> Chase Ocean Engineering Lab
> 24 Colovos Road
> Durham, NH 03824
> e: vschmidt [AT] ccom.unh.edu
> m: 614.286.3726
>
>
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