Hi Eric,
> Is it possible to program the FPGA on the 7800 to poll the DIO inputs
> on a programmable frequency (i.e., I specify), and store state change
> counts in a FIFO buffer?
>
> I need to poll the inputs at-least as fast as 100hz (not Mhz), but
> instead of creating a thread and wasting cpu cycles to accomplish
> this, I'd like the FPGA to do the polling, then I'll poll the FIFO
> (maybe 10hz or 1hz, or even every 10 seconds... considerably less
> frequently than the FPGA).
>
> *2 Questions:*
> 1) Is this technically possible / plausible
Yes.
> 2) Who can I pay to accomplish this?
Technologic have not released an open-cores design for the
TS-7800. There was some discussion on this list a few weeks
back. I can't recall if someone received an official quote
from TS on what it would take to get them to complete the
design; check the list emails, and then ask them.
100Hz sampling by the CPU is not really going to consume that
that many CPU cycles. Have you tried setting up a timer, and
reading the DIOs directly. If you have that information,
then you can make a more informed decision. Your device driver
could read the DIOs every 100Hz, write the values to a
ring-buffer, and a user-space application could read from
the buffer every 1s, or 10s.
Cheers,
Dave
------------------------------------
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> Your email settings:
Individual Email | Traditional
<*> To change settings online go to:
http://groups.yahoo.com/group/ts-7000/join
(Yahoo! ID required)
<*> To change settings via email:
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|