Thanks to Charlie (previous replier) and Oliver.
I plan to use Oliver's idea for a start and try the I2S on SSP Mode.
This way, I can use the SSP pins to talk to the DAC using I2S. I am
still a bit wary of the MCLK that the 4341A DAC requires (It needs it
for the internal operation of the 'Delta-Sigma' modulator and
interpolation filters).
I plan to share the SCLK1 out from the EP9302 with the MCLK and SCLK
of the 4341A. (Not sure if I can share this simply by connecting this
pin to two different pins of the DAC)
The double speed mode and the quad speed mode in the 4341A allow for a
128x ratio b/w MCLK and LRCK. And the EP9302 allows the bit clock
generation at 128x the LRCK. So, the DAC will be seeing the following
frequencies in the appropriate pins.
LRCK
MCLK = 128xLRCK
SCLK = MCLK = 128xLRCK
I am not sure if the DAC would puke if MCLK is same as SCLK. I don't
see it in the 4341A datasheet.
If any of you think I am crazy or you think this may actually work,
please let me know. Your comments and suggestions are greatly appreciated!
Thanks,
-Vijay
--- In Oliver Martin <> wrote:
>
> Vijay schrieb:
> > Hi friends,
> > Sorry if this has been answered already. I am using a TS-7250 and a
> > Cirrus Logic CS4341A DAC. I am trying to connect the two using an I2S
> > bus. But, looks like the Ts-7250 does not export any of the I2S pins
> > to an external header pin. [ I am just prototyping right now ]
> >
> > Namely,
> > PIN 154 - ARST
> > PIN 107 - ABITCLK
> > PIN 89 - ASYNC
> > PIN 156 - ASDI
> > PIN 92 - ASDO
>
> If you can get by without the I2S master clock, you can map the I2S
> signals to the SPI pins, which are brought out. I'm not sure if you
need
> the master clock if you want to be an I2S master - there are frame and
> bit clocks too, maybe that's enough. I only used it in slave mode, so I
> don't know. Check the EP9301 manual, there's a chapter on the I2S
> controller.
>
> Oliver
>
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