Hi guys:
I am currently trying to set the built-in ADC in the ARM EP9302
processor to collect samples at its highest -> 3750 samples per
second. According to the EP9302 manual, I have to enable the ADIV bit
in the ADCCLKDIV register which is bit 16 to either 0 or 1.
Why 0 or 1. Because I am not sure either 0 or 1. There were two EP9302
manuals that I have been studying, One is the EP93xx family manual and
the second one is EP9302 manual, they were talking differently to each
other regarding to this issue, one said enable 0 and the other said
enable 1. So I started testing it myself. However, either I enabled 1
or 0, it still gave me the same result. I have attached the init_ADC
function below, this is the bit that I have added:
//Enable ADIV bit to 1 in able to get the higest sample rate
val = PEEK32(syscon_page + ADCCLKDIV_OFFSET);
POKE32(syscon_page + SYSCON_UNLOCK, UNLOCK_VAL);
POKE32(syscon_page + ADCCLKDIV_OFFSET, val & ~0x10000);
Have I done anything wrong with it or I have misunderstand the manuals
? If I did something wrong please indicate me. Thanks a lot guys.
Full init_ADC function:
void init_ADC(unsigned long adc_page, unsigned long syscon_page)
{
unsigned long val;
/* set TSEN bit */
val = PEEK32(syscon_page + ADCCLKDIV_OFFSET);
//unlock the software lock
POKE32(syscon_page + SYSCON_UNLOCK, UNLOCK_VAL);
POKE32(syscon_page + ADCCLKDIV_OFFSET, TSEN_MASK | val);
//Enable ADIV bit to 1 in able to get the higest sample rate
val = PEEK32(syscon_page + ADCCLKDIV_OFFSET);
POKE32(syscon_page + SYSCON_UNLOCK, UNLOCK_VAL);
POKE32(syscon_page + ADCCLKDIV_OFFSET, val & ~0x10000);
/* set ADCEN bit */
val = PEEK32(syscon_page + DEVICECFG_OFFSET);
POKE32(adc_page + SYSCON_UNLOCK, UNLOCK_VAL); //unlock the soft lock
POKE32(syscon_page + DEVICECFG_OFFSET, val | ADCEN_MASK);
/* clear ADCPD bit */
val = PEEK32(syscon_page + DEVICECFG_OFFSET);
POKE32(adc_page + SYSCON_UNLOCK, UNLOCK_VAL); //unlock the soft lock
POKE32(syscon_page + DEVICECFG_OFFSET, val & ~ADCPD_MASK);
}
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