Hi Michael-
The table you posted for the amount of power saved by turning the clock speed
down is
very useful for optomizing power consumption vs clockspeed. In addition to the
incremental savings, I'm curious what the TOTAL power draw is in each of those
states.
Do you by any chance have those figures in your notes?
We are trying to decide between the 7260 and the 7400. Do you know if turning
down the
clock can be done on both boards?
Thanks,
Peter
--- In "Michael Schmidt" <> wrote:
>
> >
> > Yes, dividing down the PLL clocks. I've never played with running the
> > CPU will PLL disabled.
> >
> > It was sometime ago, but my notes state...
> >
> > pll1_ps=3 Fclkdiv=4 Hclkdiv=7 => Fclk=2594KHz Hclk=1297KHz Pclk=648KHz
> > # clkset1=0x08f7fa5a
> > static current consumption 0.24A (etheroff=0.16A)
> >
> > cheers
> > Jim
>
> Hmm, interesting. Something about shutting off the PLLs seems to save a lot
> more power I think. We measured the power drain on the TS-7400 at the
> above 2.594Mhz clock and only saw a savings of about 50mW. To compare,
> here is how much you incrementally save for each drop in Mhz:
> 250mW (0.05A) 166->200Mhz (7.4mW/Mhz)
> 200mW (0.04A) 41.5->166Mhz (1.6mW/Mhz)
> 300mW (0.06A) 14.7->41.5Mhz (11.2mW/Mhz)
> 50mW (0.01A) 2.594->14.7Mhz (4.1mW/Mhz)
>
> It appears that you get a big savings initially (due to power consumption
> being related to the square of the frequency I suppose) and then it drops
> way off, until you turn off the PLLs which appears to save at least 250mW by
> itself. I'm not sure why dropping below the clock frequency is actually
> saving more power per Mhz, unless perhaps it's just measurement/rounding
> error, but in any case there aren't enough Mhz left for it to make much
> difference...
>
> Regards,
>
> Michael
>
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