Has any one attempted to use the OpenCore verilog ts7300_top by calling
it from a VHDL wrapper file? I have a fare amount of experience with
VHDL code, no experience with verilog. My goal is to write a custom
FPGA bitstream and I wanted to use VHDL to write the custom portions. I
did want to use the bus between the ARM and Cyclone, and access pins on
the 40 pin header. I didn't want to have to convert the existing files
to VHDL, or worse yet, have to learn verilog (*yikes*).
>From Google poking it appears Quartus should support the VHDL/verilog
mix. Just wanted to see if anyone else has attemped this before and can
offer some pointers. Thanks in advance.
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