Were any features from the standard FPGA bitstream removed?
--- In "Jesse Off" <> wrote:
>
> A new experimental bitstream and kernel module is available for the TS-
> 7300 enabling 800x600 resolution and transparent bitblt'ing.
>
> ftp://ftp.embeddedARM.com/ts7300_cyclone2_800x600.rbf
> ftp://ftp.embeddedARM.com/ts7300fb-800x600.o
>
> The transparent bitblt'ing is enabled by bit 12 of the vidctrl register
> at 0x72000038. When 1, bit 5 of each pixel is looked at before being
> blitted. If bit 5 is 1, the pixel is blt'ed, if not, the original
> pixel is unmodified.
>
> This development work was funded by Peter Elliot.
>
> I will be documenting this more shortly.
>
> //Jesse Off
>
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