Hello everyone.
I need to stream multichannel hi-res audio (24 bits/192 kHz, 2
channels in / 8 channels out) between a PC and a remote device.
I would prefer to use Ethernet instead of USB and Firewire, because :
- the cable can be a lot longer (this is an important requirement)
- the technology is mature so you don't have to deal with buggy/
crashing PC chipsets and drivers
- driver development is a lot easier (actually there is no driver to
write, just a simple userspace program to present the remote device
as a JACK device to the linux user, reusing open source code from the
NetJACK project)
So, I like the TS-7300 because :
- There is a FPGA on-board : an ideal way to interface all my
hardware, generate and receive multiple I2S streams, build short
FIFOs which will be accesed in burst read/write by the CPU, etc
- The Ethernet controller is a work of art, I got drooling while
reading the datasheet and seeing how the hardware reads lists of
buffer pointers and does everything by itself.
- It's cheap, runs linux, is open source
- The mailing list is very active
Now, on to the questions, to determine wether or not I should buy
this board.
The device will receive/send a lot of data through the Ethernet,
using UDP protocol (no TCP). Using a dedicated ethernet cable, there
is no loss of packets, and full duplex transmission is possible.
Then this data will live for a short time in a ring buffer in RAM. I
wonder if it is better to have this ring buffer in the CPU RAM or in
the FPGA RAM. Can you offer advice ?
(By RAM I mean the SDRAM chip, not BRAM ; latency and buffer size
should be user selectable but I need at least 1 megabyte of buffer).
Finally, this data will be processed by the FPGA, run through FIFOs
using BRAM and output in I2S format.
There is a wishbone-compliant I2S core with FIFOs on Opencores.org.
This makes me happy.
The high data rate for this application (about 6 megabytes/s both
ways) poses a few problems so I need to identify the bottlenecks in
the TS-7300 before considering its use. So :
- Can the Ethernet and associated DMA handle this ? (full duplex)
- Is the linux kernel overhead tolerable when using UDP, and possibly
disabling the UDP/IP checksum calculations ? (the MAC CRC is enough)
- How many times is packet data copied around in the kernel ?
- Should I put the ring buffer in the CPU RAM or the FPGA RAM ?
- Are these RAM fast enough ?
- How fast is the link between FPGA and CPU ? I see from the
schematics that it is 16 bits with address and data multiplexed. Can
it do DMA bursts ? Will I be able to stream data fast enough ?
Of particular importance is the fact that the PC normally sends UDP
packets at regular intervals, but if the PC has to interrupt for a
few milliseconds (a disk access for instance), it will send the
backlog of UDP packets at full wire speed (100 Mbps) to catch up; so
the data path between Ethernet and Ring buffer must be able to handle
this speed.
Thanks a lot for your time !
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