[ts-7000] Re: Problem compiling FPGA code with Quartus 5.1

["aqueisser" <>]

--- In  "Jesse Off" <> wrote:
>
> I've run into this before.  Its a problem with the altpll 
> megafunction instantiation.  This is because the project is a 
> Quartus 6 project and you're using 5.1.  You can create a new pll 
> megafunction in 5.1 if you want -- the FPGA logic just needs for you 
> to create 75Mhz from 25Mhz.
> 
> //Jesse Off
> 

Jesse, 

thanks for the tip - worked like a charm.

Andrew








 
Yahoo! Groups Links

<*> To visit your group on the web, go to:
    http://groups.yahoo.com/group/ts-7000/

<*> Your email settings:
    Individual Email | Traditional

<*> To change settings online go to:
    http://groups.yahoo.com/group/ts-7000/join
    (Yahoo! ID required)

<*> To change settings via email:
     
    

<*> To unsubscribe from this group, send an email to:
    

<*> Your use of Yahoo! Groups is subject to:
    http://docs.yahoo.com/info/terms/