Jesse,
Thanks for posting the FPGA template, I'm no doubt going to spend
hours trying to making a single LED flash! ;).
Could you clarify the issues relating to the getting access to the TS-
cores such as VIDEO, SD, XDIO. If I wanted to make a custom FPGA
image containing Technologic Systems non-GPL code. In my application
I need the Video, SD and Ethernet but would roll my own IO block.
Regards,
Peter
--- In "Jesse Off" <> wrote:
>
> All,
>
> We've just released a boilerplate Quartus II project complete with
> Verilog source code, pin locks, pll settings, and timing
constraints
> for the TS-7300 FPGA in the files section of this group. The
project
> can be compiled with Altera's free web-edition FPGA tools. Quite a
> bit of the documentation of this design is contained in the Verilog
> comments, so I won't rehash them here--.
>
> This should be all you need to begin experimentation on a custom
FPGA
> design with the TS-7300. My hope is that this will allow an avenue
> for interested people to create a diverse set of hardware
> functionality that all customers can share. It also was somewhat
> designed with the intent to be used in a classroom environment for
> learning FPGA's, Verilog, WISHBONE and embedded systems design using
> both a CPU and an FPGA.
>
> Included in this skeleton project is some bus-cycle demultiplexing
> logic that bridges the CPU <-> FPGA bus cycles into a WISHBONE
> interface. The WISHBONE bus has 3 slave cores connected- one stub
> core for user logic, one for the ethernet, and one for the ethernet
> packet RAM. You should be able to just download the .zip, double-
> click the Quartus II project file, click the compile button and
have a
> working ts7300_top.rbf bitstream file that can be installed to the
> FPGA with the load_ts7300 command (no JTAG/ISP cables).
>
> //Jesse Off
>
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