[ts-7000] Does the 7260 TS-XDIO option REPLACE basic DIO address space and Direction logic

["xioaya12" <>]

Concerning the  TS-7260, if it was ordered STANDARD with TS-XDIO 
feature. 
(NOT with the SD Card Socket option or the 2 extra TTL serial ports 
option)

Then the basic DIO2 where: 
        0x12C0_0000 - is data
        0x12C0_0001 - is direction  (where 1 is output).

Is REPLACED with the TS-XDIO core, where (from Table: TS-XDIO):
        0x12C0_0000 - is mode
        0x12C0_0001 - is direction  (if mode = 0x0);  (where 0 is 
output).
        0x12C0_0002 - is data (if mode = 0x0);
        0x12C0_0003 - is not used (if mode = 0x0);
This assumes that the register 0-3 are contiguous starting at 
0x12C0_0000.

It was not clear that mode and data changed addresses between the 
two configurations
AND that direction had changed logic level as well (for mode 0x0);

   To simply configure DXIO2 w/ TS_XDIO Header 2 as all outputs: 
<snip>
   startDio = mmap(0, getpagesize(), PROT_READ|PROT_WRITE, 
MAP_SHARED, fd, 0x12C0_0000);
   dioMode = (unsigned int *)(startDio);      
   dioDir = (unsigned int *)(startDio + 0x01);     
   dioData = (unsigned int *)(startDio + 0x02);  
   dioIrq = (unsigned int *)(startDio + 0x03);  
  
   *dioMode = 0x0;  // bits 7-6 sets this up to be a simple data IO 
mode, other bits not used
   *dioDir = 0x0;       // all bits set as output  (not sure about 
this, flipped from standard logic ???)
   *dioIrq = 0x0;       // not used, but initialized to zero (OK ???)

   for(i = 0; i < 10; i++) {      // set all outputs high, wait, set 
low, wait, repeat 10 times.
        *dioData = 0xff;
        usleep(17500);
        *dioData = 0x00;
        usleep(17500);
   }
</snip>
====================sections of 7260 User Manual ==================

7260 Manual
pg 20, Section 4.2, pp 2
The DDR controls whether each DIO pin is an input or an output ("1" 
= output). Writing
to the data register only affects pins that are configured as 
outputs.

pg 21, Section 5.8, pp 2
There is a Digital IO capability implemented at 0x12C0_0000. The 
following
register map describes the behavior of this feature.
0x0     Data Register   1 - Pin at logic high
                        0 - logic low
0x1     Data Direction reg      1 - output
                        0 - input
Bits of each register correspond to pin X * 2 + 1 on the DIO2 header.

pg 30, Section 5.8 pp TS-XDIO
The TS-XDIO core appears at the address locations 0x12C0_0000-
0x12C0_0003...
...
The TS-XDIO functionality can be controlled through 4 control/status 
registers that
appear at physical memory.

pg 46 Appendix B: Memory and Register Map
0x12C0_0000 - 0x12C0_0003       (TS-7260) DIO2 Header XDIO registers
0x12C0_0000 - 0x12C0_0001       (TS-7260) DIO2 Basic XDIO registers







 
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