Jim,
There is a register at 0x80060008 that contains the number of HCLK
periods between issueing the AUTO-REFRESH SDRAM cycle. On the 32MB
chips used on the TS-7xxx, this needs to happen 8192 times every 64mS.
If you're really paranoid about running at extreme high temperatures,
you can set this higher than normal. Setting this to a higher rate
than normal and clocking down the CPU will significantly increase the
highest safe temperature. (if you're not using ethernet... otherwise..
the ethernet PHY is the weakest link thermally)
//Jesse Off
--- In Jim Jackson <> wrote:
>
>
>
>
> On Thu, 13 Apr 2006, Jesse Off wrote:
>
> > Also, for those using Jim Jackson's cctl program to modify the PLL
> > registers, be warned that I don't think it currently changes the
> > refresh rate of the SDRAM when it lowers the HCLK. The SDRAM won't
> > get refreshed often enough at the slow clock rates and you'll have a
> > board that will work most of the time, but may start exhibiting random
> > memory corruption-- esp. in high temperature environments where the
> > SDRAM capacitor leakage is greater.
>
> Jesse is correct, and the warning is timely. I've not looked at what
needs
> doing for the refresh rate. If anyone can tell me what needs doing I'll
> mod the cctl program. At the moment I've quite a bit on, so will need an
> "in" as to what to do.
>
> If anyone modifies cctl please let me know what you've done, so I can
> incorporate the changes etc.
>
>
> cheers
> Jim
>
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