We have measured 220 mW power with an input voltage of 5.0V, ethernet
PHY turned off, and both PLL1 and PLL2 bypassed (clkset1.nbyp1=0,
clkset2.nbyp2=0 -- CPU running at 14.7Mhz), LED's off, RS232 level
converter on and 1 serial port plugged into a PC via 6ft null modem
cable. The board tested was a board with 64MB SDRAM + RTC chip with
nothing plugged into USB. I was able to get 200mW (40 mA at 5V) on a
board with only 32MB and no RTC. The board was booted to the default
Linux install and was idling at a command prompt. It is possible to
save a bit more power by turning off the RS232 level converters and
maybe also by slowing the 100Hz Linux clock tick down. If Linux could
do it, the CPU can put the SDRAM chips in self-refresh mode for even
more power savings when idle.
Unfortunately, the switcher IC we are using seems to exhibit
significantly less efficiency as the voltage goes up. The low
voltages seem best. We're looking into this with the IC manufacturer.
I remember talking to another customer awhile ago and he found that
lowering the HCLK was the biggest power-saver next to turning off
ethernet. The ARM9 CPU core is already very power efficient and
lowering its clock rate (FCLK) had little effect on an idle board.
Ethernet is a huge power hog and there are big gains to be had if the
PHY is switched off. A good improvement Linux could make here would
be to keep the PHY turned off, and momentarily turn it on every 5-10
seconds to check for link. The Micrel PHY has a neat "energy detect"
bit that can be polled very quickly after turn-on for a good
indication of whether the ethernet is plugged in or not. Normally,
you might have to initiate a ethernet PHY autonegotiation which can
take several seconds to detect link, but instead that bit could be
quickly polled and the PHY could be shut down another 10 seconds if
there is no cable (or on 'ifconfig eth0 down').
Something similar could be done for the serial ports. If no process
has the serial port open, the RS232 converter may as well be shut down.
Also, for those using Jim Jackson's cctl program to modify the PLL
registers, be warned that I don't think it currently changes the
refresh rate of the SDRAM when it lowers the HCLK. The SDRAM won't
get refreshed often enough at the slow clock rates and you'll have a
board that will work most of the time, but may start exhibiting random
memory corruption-- esp. in high temperature environments where the
SDRAM capacitor leakage is greater.
//Jesse Off
--- In "inc" <> wrote:
>
> Hello,
> I am also very interested in the 1/4 watt mode of operation, have
> you received any help with this ? Have you had any luck manipulating
> the power management register on the TS7260 ?
>
> Len.
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