> Maybe future versions of the board could have multiple user SPI chip
selects
> coming from the CPLD. (just an idea)
>
> -Curtis.
>
You could use any of the GPIO lines for that. Thats how the EEPROM CS
actually works.
1) CS to the EEPROM is manually asserted from a GPIO line
2) SPI transmit fifo is primed by CPU
3) SPI is enabled, SPI clock runs and TX fifo empties/RX fifo fills
4) receive fifo is emptied by CPU
5) CS is deasserted
The SPI frame signal from the EP9302 also can be used though its exact
semantics depend on the SPI mode and may or may not be what you
actually want to connect to your SPI device's CS. You could use an
external AND gate between a GPIO and the frame signal if you do need
the exact timing of the EP9302's SPI frame signal and want to use
multiple SPI devices.
//Jesse Off
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