[ts-7000] pc/104 bus timings

["pickanameanditstakensoihavethis" <>]

hi  
 
im trying to suport the std pc/104 bus as well as the ts7200 use of 
the bus  
 
ok so got most of the circuit sorted but i have a slight problem  
 
driving a 8 bit latch from the data bus 
 
the pc104 timing would require the   IOR# ,BALE and I/OCHRDY to be 
low ( along with the correct address)  
 
on the ts7200 there is only the  IOR# line  
 
according to the pc104 spec the data is valid on I/OCHRDY  
and not on the falling edge of IOR#  
 
so when operating with the ts7200 how would i best detect the data 
as being valid  
 
also  how does the ts7200 handle the generation of memr / memwr over  
ior/ iow  accesses are these in a seperate space ?  
 
i need to ensure correct operation between ether std pc104 or the 
ts7200  
to support the ts7200 10 bit data use  i have used 8 0R resistors 
that are fitted if the 16 bit connector is not allowing for the 
ts7200 configuration , i dont want to add to many other 0r resistors 
for this   
 
so is there a simple solution like  making the logic cope with BALE, 
and I/OCHRDY  but linking them out for use on the TS7200 
 
 
if i have the correct idea of the ts7200's method then data would be 
valid on iow# or memw#  along with the address being valid for the 
location of the device  
 
Dave  





 
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