--- In "Jesse Off" <> wrote:
> Also, since we scrapped the high static power Xilinx CPLD for a lower
> power Altera CPLD with a lot more space for custom logic, we've
> included a third serial port and an extra 10 pins of DIO. The boards
> can be built with one of a few logic loads, one of them puts 2 more
> serial UARTS (total 5: 3 off-CPU, 2 on-CPU) and the other includes
> something we've dubbed the TS-XDIO port. There are more in development.
>
> The TS-XDIO is like regular DIO port (data direction register and data
> register), but includes some other cute features that can be difficult
> or very inefficient to do in software. The port can read quadrature
> (and IRQ on direction change for min/max quadrature counts), output
> PWM or finite length pulses, and also measure frequency or pulse times
> with 67nS accuracy. You can also just internally loop the PWM
> generator to the pulse timer and have a free-running 14.7456Mhz
> counter for high resolution timestamping. (The on-CPU debug4 timer
> only runs at 983kHz)
WOW! I want one! Seriously, if I read this correctly, this should
make implementing things like LIRC fairly easy. LIRC (Linux Infra Red
Receiver - http://www.lirc.org ) needs accurate timed pulses from an
IR receiver. The existing board won't do both leading and trailing
edge IRQs so it's hard to implement. Basically LIRC needs a timed
train of on-off data to interpret TV remotes...
Is there a spec/manual available yet?
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