[ts-7000] TS-7300 verilog for making FPGA default bit-stream.

To:
Subject:	[ts-7000] TS-7300 verilog for making FPGA default bit-stream.
From:	"Sungjoon" <>
Date:	Wed, 23 Nov 2011 02:05:38 -0000

Hi,

Does anyone have verilog files that can generate default bit stream for the 
TS-7300's FPGA?

I want to disable the video output and use those ports for general I/O while 
maintaing the other functions such as serial ports. 

Thanks

Sungjoon 



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