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I was able to add encryption to the 7500 utilizing the unused on-board flash, if that helps Walter From: jesseoff <> To: Sent: Thursday, September 1, 2011 6:01 PM Subject: [ts-7000] Re: TS-7550 XUARTs --- In , mike ingle <> wrote: > > Hi Jesse, > > thank you for the detailed response. I am a fan of user space drivers and big hardware buffers, for the same reasons you outlined, I just wanted to make sure that there weren't any gotcha's present. While I maybe have your attention, what is the usability of the FPGAs for user reconfiguration on: > > ts 7500 sd on fpga > ts 7550 xnand no sd on fpga > ts 4500 xnand sd on fpga > > i am considering all of the above as possible solutions. I tend to want to add tools to my toolbox, and would like to settle on a board I can use for future projects as well. With the lattice fpga can you offer encrypted modules, allowing the user to have their own IP and still have the sd and xuart functionality? All those three boards have what we call "open cores" available for download: ftp://ftp.embeddedarm.com/ts-arm-sbc/ts-7500-linux/sources/ts75xx_opencores_src_diamond_aug052011.tar.gz The above tarball includes pre-configured Lattice Diamond FPGA project files for each of the types of boards listed. The projects uses a few binary "black box" .ngo modules for the SD, NAND, and XUART cores, but everything else has full Verilog source code. These projects compile right out of the box and will create a .jed JEDEC file that can be loaded on board startup via the command "ts7500ctl --loadfpga foo.jed". Although it can use the .jed, we recommend first converting it to a .vme.gz with the "jed2vme" utility we've written as then the fpga reload file is only 90-120kbyte and can fit on the initrd. The "ts7500ctl --loadfpga" command can take a .jed, .vme, or .vme.gz. Reloading the FPGA on startup requires about 3 extra seconds of boot time, and can be done at any time post-boot also. I've optimized this as far as I can and while I could feed the FPGA its new configuration faster, it seems the Lattice XP2 FPGA's don't like it. All of the userspace drivers are "fpga reload safe" since "ts7500ctl --loadfpga" will first acquire the SBUS lock thereby suspending any in progress FPGA communication and hold onto it while it lobotomizes the FPGA and reprograms it. After reprogramming, the SBUS lock is released and a SIGHUP is sent to all the userspace drivers which instructs them to reinitialize hardware state. If the number of XUART ports have grown or shrank, connections may be dropped or new listener sockets created. It is important to note that the FPGA reload is only a SRAM cell update and it does not update the XP2 on chip flash configuration. Updating the flash FPGA program can render a board unbootable, so we only do that here. During development, I've gotten my share of boards here in unbootable/unreprogrammable states where I actually had have a technician desolder some pins on the FPGA or CPU to bring the board back to life-- its not something anybody on our mailing list would want to walk a customer through. Also, although we provide these FPGA projects for free download, we have to draw the line on answering questions on them or supporting them. FPGA's are just too complicated and we're not wanting to sign up for helping engineering departments learn about FPGA's or understand our Verilog on a $89 board. This is not to say we won't help period, just we won't help for free. There is only a few of us here that can help besides the authors. >Also, in the past I have had issues using the 0.1" dual row headers, where the female connector was damaged by prying the module out at an angle (hard to do any other way), have you had issues on the ts75xx modules with that? Yeah -- the .1" male header is not the most high-tech style connector available these days. However, it is easy and cheap to repair or replace. I've talked to a few customers that have desoldered and pulled it off and soldered wires in instead. Its also common to lay out another PCB with .1" holes and solder the TS-7550 to another board. We've always liked through-hole connectors because they hold up to a lot more abuse before damaging the PCB -- a lot of the surface mount connectors will peel the copper traces from the FR4 substrate under stress. We haven't had a lot of problems with the female side, although I do remember experimenting with a lower cost female PC104 connector 5 years ago which did not use the same internal mating mechanism and had problems with male pins not from the same manufacturer. //Jesse Off __._,_.___
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