Cirrus 9301 manual shows GPIO port F being 3 bits wide - wrong for 9302! It is
apparently 8 bits wide on 9302.
The TS-7260 schematic shows IRQ7 mapped to INT2 - wrong! It is mapped to INT3
(port F, bit 3, which is marked 'rsvd' in 9301 manual), EP9302 datasheet says
"Note: INT[2] is not bonded out." on pp 9.
Apparently from what we can see both IRQ6 and IRQ7 bypass the GPIO entirely and
are only handled by the VIC.
To my sensibilities this is difficult to believe as the boards have been
shipping a long time, and some of you would know this if true. But it appears
to be true.
So I have now wire-wrapped the pins on the TS-SER2 card so that the LPT
interrupt is passed to IRQ5, which appears to be the only external interrupt
that can be set to edge-sensitive mode via GPIO.
Why anyone would build a chip that defaults to a level-sensitive interrupt
anyway? I hope I am wrong, and I hope I am right. We have spent a long time
dealing with the wrong configuration.
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